Method and apparatus for generating expect data from a captured bit pattern, and memory device using same

ABSTRACT

Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of these applied data signals have been properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated from the captured first group of applied data signals. A second group of the applied data signals are then captured after the first group. The second group of applied data signals are determined to have been properly captured when the second captured group of applied data signals corresponds to the group of expect data signals. In this way, when capture of the applied series of data signals is shifted in time from an expected initial capture point, subsequent captured groups of applied data signals are compared to their correct expected data signals in order to determine whether that group, although shifted in time, was nonetheless correctly captured. A pattern generator generates expect data signals in this manner, and this pattern generator may be utilized in a synchronization circuit to synchronize a plurality of clock signals. This pattern generator is suitable for use in synchronization circuits and a variety of integrated circuits, but is particularly well-suited for synchronizing command and data clocks applied to SLDRAMs.

TECHNICAL FIELD

[0001] The present invention relates generally to integrated circuitdevices, and more particularly to a method and circuit utilizing a firstcaptured bit stream in generating expect data for subsequent capturedbit streams.

BACKGROUND OF THE INVENTION

[0002] A conventional computer system includes a processor coupled to avariety of memory devices, including read-only memories (“ROMs”) whichtraditionally store instructions for the processor, and a system memoryto which the processor may write data and from which the processor mayread data. The system memory generally includes dynamic random accessmemory (“DRAM”), and in many modern computer systems includessynchronous DRAMs (“SDRAMs”) to enable the processor to access data atincreasingly faster rates. One skilled in the art will appreciate,however, that a large speed disparity subsists between the operatingspeed of modern processors and that of modern SDRAMs. This speeddisparity limits the rate at which the processor can access data storedin the SDRAMs, which is a common operation, and consequently limits theoverall performance of the computer system. For example, modemprocessors, such as the Pentium® and Pentium II® microprocessors, arecurrently available operating at clock speeds of at least 400 MHz, whilemany SDRAMs operate at a clock speed of 66 MHz, which is a typical clockfrequency for controlling system memory devices.

[0003] A solution to this operating speed disparity has been proposed inthe form of a computer architecture known as a synchronous linkarchitecture. In the synchronous link architecture, the system memorydevices operate at much higher speeds and may be coupled to theprocessor either directly through the processor bus or through a memorycontroller. Rather than requiring that separate address and controlsignals be provided to the system memory, synchronous link memorydevices receive command packets that include both control and addressinformation. The synchronous link memory device then outputs or receivesdata on a data bus that may be coupled directly to the data bus portionof the processor bus.

[0004] A typical synchronous link dynamic random access memory(“SLDRAM”) memory device 16 is shown in block diagram form in FIG. 1.The memory device 16 includes a clock generator circuit 40 that receivesa command clock signal CCLK and generates a large number of other clockand timing signals to control the timing of various operations in thememory device 16. The memory device 16 also includes a command buffer 46and an address capture circuit 48 which receive an internal clock signalICLK, a command packet CA<0:39> in the form of 4 packet words CA<0:9>applied sequentially on a 10 bit command-address bus CA, and a terminal52 receiving a FLAG signal. A synchronization circuit 49 is part of thecommand buffer 46, and operates during a synchronization mode tosynchronize the command clock signal CCLK and two data clock signalsDCLK0 and DCLK1 as will be explained in more detail below.

[0005] A memory controller (not shown) or other device normallytransmits the command packet CA<0:39> to the memory device 16 insynchronism with the command clock signal CCLK. The command packetCA<0:39> contains control and address information for each memorytransfer. The FLAG signal identifies the start of a command packetCA<0:39>, and also signals the start of an synchronization sequence. Thecommand buffer 46 receives the command packet CA<0:39> from thecommand-address bus CA, and compares at least a portion of the commandpacket to identifying data from an ID register 56 to determine if thecommand packet is directed to the memory device 16 or some other memorydevice (not shown). If the command buffer 46 determines that the commandis directed to the memory device 16, it then provides the command to acommand decoder and sequencer 60. The command decoder and sequencer 60generates a large number of internal control signals to control theoperation of the memory device 16 during a memory transfer.

[0006] The address capture circuit 48 also receives the command packetfrom the command-address bus CA and outputs a 20-bit addresscorresponding to the address information in the command packet. Theaddress is provided to an address sequencer 64, which generates acorresponding 3-bit bank address on bus 66, a 10-bit row address on bus68, and a 7-bit column address on bus 70. The row and column addressesare processed by row and column address paths, as will be described inmore detail below.

[0007] One of the problems of conventional DRAMs is their relatively lowspeed resulting from the time required to precharge and equilibratecircuitry in the DRAM array The memory device 16 largely avoids thisproblem by using a plurality of memory banks 80, in this case eightmemory banks 80 a-h. After a read from one bank 80 a, the bank 80 a canbe precharged while the remaining banks 80 b-h are being accessed. Eachof the memory banks 80 a-h receives a row address from a respective rowlatch/decoder/driver 82 a-h. All of the row latch/decoder/drivers 82 a-hreceive the same row address from a predecoder 84 which, in turn,receives a row address from either a row address register 86 or arefresh counter 88 as determined by a multiplexer 90. However, only oneof the row latch/decoder/drivers 82 a-h is active at any one time asdetermined by bank control logic 94 as a function of a bank address froma bank address register 96.

[0008] The column address on bus 70 is applied to a column latch/decoder100, which supplies I/O gating signals to an I/O gating circuit 102. TheI/O gating circuit 102 interfaces with columns of the memory banks 80a-h through sense amplifiers 104. Data is coupled to or from the memorybanks 80 a-h through the sense amps 104 and I/O gating circuit 102 to adata path subsystem 108 which includes a read data path 110 and a writedata path 112. The read data path 110 includes a read latch 120 thatstores data from the I/O gating circuit 102. In the memory device 16, 64bits of data, which is designated a data packet, are stored in the readlatch 120. The read latch then provides four 16-bit data words to anoutput multiplexer 122 that sequentially supplies each of the 16-bitdata words to a read FIFO buffer 124. Successive 16-bit data words areclocked into the read FIFO buffer 124 by a clock signal RCLK generatedfrom the internal clock signal ICLK. The 16-bit data words are thenclocked out of the read FIFO buffer 124 by a clock signal obtained bycoupling the RCLK signal through a programmable delay circuit 126. Theprogrammable delay circuit 126 is programmed during synchronization ofthe memory device 16 so that the data from the memory device is receivedby a memory controller, processor, or other device (not shown) at theproper time. The FIFO buffer 124 sequentially applies the 16-bit datawords to a driver circuit 128 which, in turn, applies the 16-bit datawords to a data bus DQ. The driver circuit 128 also applies one of twodata clock signals DCLK0 and DCLK1 to respective data clock lines 132and 133. The data clocks DCLK0 and DCLK1 enable a device, such as aprocessor, reading the data on the data bus DQ to be synchronized withthe data. Particular bits in the command portion of the command packetCA<0:39> determine which of the two data clocks DCLK0 and DCLK1 isapplied by the driver circuit 128. It should be noted that the dataclocks DCLK0 and DCLK1 are differential clock signals, each includingtrue and complementary signals, but for ease of explanation, only onesignal for each clock is illustrated and described.

[0009] The write data path 112 includes a receiver buffer 140 coupled tothe data bus 130. The receiver buffer 140 sequentially applies 16-bitdata words from the data bus DQ to four input registers 142, each ofwhich is selectively enabled by a signal from a clock generator circuit144. The clock generator circuit 144 generates these enable signalsresponsive to the selected one of the data clock signals DCLK0 andDCLK1. The memory controller or processor determines which data clockDCLK0 or DCLK1 will be utilized during a write operation using thecommand portion of a command packet applied to the memory device 16. Aswith the command clock signal CCLK and command packet CA<0:39>, thememory controller or other device (not shown) normally transmits thedata to the memory device 16 in synchronism with the selected one of thedata clock signals DCLK0 and DCLK1. The clock generator 144 isprogrammed during synchronization to adjust the timing of the clocksignal applied to the input registers 142 relative to the selected oneof the data clock signals DCLK0 and DCLK1 so that the input registers142 can capture the write data at the proper times. In response to theselected data clock DCLK0 or DCLK1, the input registers 142 sequentiallystore four 16-bit data words and combine them into one 64-bit writepacket data applied to a write FIFO buffer 148. The write FIFO buffer148 is clocked by a signal from the clock generator 144 and an internalwrite clock WCLK to sequentially apply 64-bit write data to a writelatch and driver 150. The write latch and driver 150 applies the 64-bitwrite data packet to one of the memory banks 80 a-h through the I/Ogating circuit 102 and the sense amplifiers 104.

[0010] A typical command packet CA<0:39> for the SLDRAM 16 is shown inFIG. 2 and is formed by 4 packet words CA<0:9>, each of which contains10 bits of data. As explained above, each 10-bit packet word CA<0:9> isapplied on the command-address bus CA including the 10 lines CA0-CA9,and coincident with each packet word CA<0:9> a FLAG bit is applied onthe FLAG line 52. As previously discussed, during normal operation theFLAG bit is high to signal the start of a command packet CA<0:39>, andthus is only high coincident with the first packet word CA<0:9> of thecommand packet. In FIG. 2, the four packet words CA<0:9> comprising acommand packet CA<0:39> are designated PW1-PW4. The first packet wordPW₁ contains 7 bits of data identifying the memory device 16 that is theintended recipient of the command packet. The memory device 16 has aunique ID code stored in the ID register 56, and this code is comparedto the 7 ID bits in the first packet word PW₁. Thus, although all of thememory devices 16 in a synchronous link system will receive the commandpacket CA<0:39>, only the memory device 16 having an ID code thatmatches the 7 ID bits of the first packet word PW₁ will respond to thecommand packet.

[0011] The remaining 3 bits of the first packet word PW₁ as well as 3bits of the second packet word PW₂ comprise a 6 bit command. Typicalcommands are read and write in a variety of modes, such as accesses topages or banks of memory cells. The remaining 7 bits of the secondpacket word PW₂ and portions of the third and fourth packet words PW₃and PW₄ comprise a 20 bit address specifying a bank, row and columnaddress for a memory transfer or the start of a multiple bit memorytransfer. In one embodiment, the 20-bit address is divided into 3 bitsof bank address, 10 bits of row address, and 7 bits of column address.Although the command packet CA<0:39> shown in FIG. 2 is composed of 4packet words PW1-PW4 each containing up to 10 bits, it will beunderstood that a command packet may contain a lesser or greater numberof packet words, and each packet word may contain a lesser or greaternumber of bits.

[0012] As mentioned above, an -important goal of the synchronous linkarchitecture is to allow data transfer between a processor and a memorydevice to occur at a significantly faster rate. However, as the rate ofdata transfer increases, it becomes more difficult to maintainsynchronization between signals transmitted to the memory device 16. Forexample, as mentioned above, the command packet CA<0:39> is normallytransmitted to the memory device 16 in synchronism with the commandclock signal CCLK, and the data is normally transmitted to the memorydevice 16 in synchronism with the selected one of the data clock signalsDCLK0 and DCLK1. However, because of unequal signal delays and otherfactors, the command packet CA<0:39> may not arrive at the memory device16 in synchronism with the command clock signal CCLK, and the data maynot arrive at the memory device 16 in synchronism with the selected dataclock signal DCLK0 or DCLK1. Moreover, even if these signals areactually coupled to the memory device 16 in synchronism with each other,they may loose synchronism once they are coupled to circuits within thememory device. For example, internal signals require time to propagateto various circuitry in the memory device 16, differences in the lengthsof signal routes can cause differences in the times at which signalsreach the circuitry, and differences in capacitive loading of signallines can also cause differences in the times at which signals reach thecircuitry. These differences in arrival times can become significant athigh speeds of operation and eventually limit the operating speed ofmemory devices.

[0013] The problems associated with varying arrival times areexacerbated as timing tolerances become more restricted with higher datatransfer rates. For example, if the internal clock ICLK derived from thecommand clock CCLK does not latch each of the packet words CA<0:9>comprising a command packet CA<0:39> at the proper time, errors in theoperation of the memory device may result. Similarly, data errors mayresult if internal signals developed responsive to the data clocks DCLK0and DCLK1 do not latch data applied on the data bus DQ at the propertime. Thus, the command clock CCLK and data clocks DCLK0 and DCLK1 mustbe synchronized to ensure proper operation of the SLDRAM 16. One skilledin the art will understand that when synchronization of the clocksignals CCLK, DCLK0, and DCLK1 is discussed, this means the adjusting ofthe timing of respective internal clock signals derived from theserespective external clock signals so the internal clock signals can beused to latch corresponding digital signals at optimum times. Forexample, the command clock signal CCLK is synchronized when the timingof the internal clock signal ICLK relative to the command clock signalCCLK causes packet words CA<0:9> to be latched at the optimum time.

[0014] To synchronize the clock signals CCLK, DCLK0, and DCLK1, thememory controller (not shown) places the memory device 16 in asynchronization mode by applying a 15 bit repeating pseudo-random bitsequence on each line of the command-address bus CA, data bus DQ, and onthe FLAG line 52. One of the 15 bit pseudo-random bit sequences that maybe applied is shown below in Table 1: TABLE 1 FLAG 1 1 1 1 0 1 0 1 1 0 01 0 0 0 CA<9> 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 CA<8> 1 1 1 1 0 1 0 1 1 0 01 0 0 0 CA<7> 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 M M M M M M M M M M M M M MM M CA<0> 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 DQ<15> 0 0 0 0 1 0 1 0 0 1 1 0 11 1 DQ<14> 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 M M M M M M M M M M M M M M M MDQ<0> 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0

[0015] As seen in Table 1, the 15-bit pseudo-random bit sequence iscomplemented on adjacent lines of the command-address bus CA and databus DQ. In the following description, only the synchronization of theICLK signal will be described, so only the bit sequences applied on thecommand-address bus CA and FLAG line 52, which are latched in responseto the ICLK signal, will be discussed. Furthermore,.the bit sequencesapplied on the comnmand-address bus CA and FLAG line 52 mayalternatively be referred to as bit streams in the following discussion.However, the DCLK0 and DCLK1 signals are synchronized in essentially thesame manner.

[0016] The memory device 16 captures the bits applied on the linesCA0-CA9 and the FLAG line 52 in response to the ICLK signal, and thesynchronization circuit 49 places the memory device 16 in thesynchronization mode when it detects two consecutive high (i.e., two1's) on the FLAG bit. Recall, during normal operation, only a singlehigh FLAG bit is applied coincident with the first packet word CA<0:9>of the command packet CA<0:39>. After the synchronization circuit 49places the SLDRAM 16 in the synchronization mode, the SLDRAM 16continues capturing packet words CA<0:9> applied on the bus CA and thecoincident applied FLAG bits in response to the ICLK signal. After fourpacket words CA<0:9> and the accompanying four FLAG bits have beencaptured, the synchronization circuit 49 compares the captured bits totheir expected values. The synchronization circuit 49 determines theexpected values from the known values of the 15 bit repeatingpseudo-random bit sequence. For example, from Table 1, after the firstfour bits 1111 of the FLAG bit are captured, the circuit 49 calculatesthe expected data for the next four captured bits as 0101, and the nextfour as 1001, and so on. In operation, the synchronization circuit 49adjusts the phase of the ICLK signal before capturing the next group ofbits. For example, a first phase for the ICLK signal is used to capturethe first four FLAG bits 1111, a second phase for the FLAG bits 0101, athird phase for the FLAG bits 1001. and so on. Each phase resulting insuccessful capture of the command packet CA<0:39> is recorded by thesynchronization circuit 49, and thereafter one of these phases isselected to be utilized during normal operation of the memory device 16.

[0017]FIG. 3 illustrates a potential problem encountered whensynchronizing the memory device 16 as described above. In FIG. 3, the15-bit pseudo-random bit pattern applied for the FLAG bit is shown byway of example, but the same potential problem exists for the bitsequences on the lines CA0-CA9 as well. The top sequence is the actualbit pattern applied for the FLAG bit, with the bits arranged in groupsof 4 in respective capture groups C1-C15. Each capture group C1-C15corresponds to the four FLAG bits captured coincident with fourcorresponding packet words CA<0:9>. The capture group C1 corresponds tothe start of the bit sequence, and, as should be noted, the twoconsecutive ones for the FLAG bit place the memory device 16 in thesynchronization mode. Ideally, the SLDRAM 16 captures the first group C1of 4 FLAG bits 1111, then the group C2 of 0101, then group C3 of 1001,and so on. During ideal operation, the capture group C1 of 1111 iscaptured first, placing the memory device 16 in synchronization mode,and thereafter, the synchronization circuit 49 (FIG. 1) provides theexpected data for the subsequent capture groups C2-CN. In other words,the synchronization circuit 49 expects the captured FLAG bits for C2 toequal 0101, for C3 to equal 1001, and so on.

[0018] If the capturing of the FLAG bit sequence is shifted, however, asshown in the lower bit sequence of FIG. 3, the synchronization circuit49 may use the improper expect data for capture groups C2-C15. Forexample, assume the actual bits captured for groups C1-C5 are as shownin the lower bit sequence of FIG. 3. In response to the bits 1101captured for group C1, the memory device 16 enters the synchronizationmode of operation due to the two high FLAG bits. After this, thesynchronization circuit 49 expects group C2 bits to equal 0101, group C3bits to equal 1001, and so on for groups C4-C15 as indicated by theideal FLAG data shown in the top bit sequence. Instead, however, thegroup C2 bits equal 0110 for the shifted FLAG sequence, and the group C3equals 0100, and so on, such that each of the respective capture groupsC1-C15 in the shifted FLAG bit sequence corresponds to four bits in thetop bit sequence shifted to the left by two bits, as indicated by dottedlines 30. This could occur, for example, when the memory device 16 failsto latch the first two ones applied on the FLAG line 52 due to delays inCCLK signal applied by the controller. When the FLAG bit sequence isshifted, the values of subsequent capture groups result in thesynchronization circuit 49 determining the FLAG bit is not beingcorrectly captured, when in fact the FLAG bit pattern is beingsuccessfully captured but is merely shifted by a random number of bits.

[0019] There is a need for generating accurate expect data whencapturing a pseudo-random bit sequence during synchronization ofpacketized memory device. In addition, it should be noted that while theabove discussion is directed towards packetized memory devices such asSLDRAMs, the concepts apply to other types of integrated circuits aswell, including other types of memory devices and communicationscircuits.

SUMMARY OF THE INVENTION

[0020] According to one aspect of the present invention, expect datasignals are generated for a series of applied data signals having aknown sequence to determine if groups of these applied data signals havebeen properly captured. A method according to one embodiment of thepresent invention captures a first group of the applied data signals,and generates a group of expect data signals from the captured firstgroup of applied data signals. A second group of the applied datasignals are then captured after the first group. The second group ofapplied data signals are determined to have been properly captured whenthe second captured group of applied data signals equals the group ofexpect data signals. In this way, when capture of the applied series ofdata signals is shifted in time from an expected initial capture point,subsequent captured groups of applied data signals are compared to theircorrect expected data signals in order to determine whether that group,although shifted in time, was nonetheless correctly captured.

[0021] According to another aspect of the present invention, the seriesof applied data signals comprises a 15-bit pseudo-random bit sequence ofdata signals. In one embodiment, this 15-bit pseudo-random bit sequencecomprises the repeating bit sequence of ‘111101011001000,’ and 4-bitgroups of this repeating pseudo-random bit sequence are captured at atime. In this embodiment, the generated expect data signals representall possible 4-bit combinations for the 15-bit pseudo-random bitsequence, these 15 possible 4-bit combinations being 1111, 0101, 1001,0001, 1110, 1011, 0010, 0011, 1101, 0110, 0100, 0111, 1010, 1100, and1000.

[0022] According to another aspect of the present invention, apacketized dynamic random access memory includes a pattern generatorthat generates expect data for a repeating bit sequence applied onexternal terminals of the memory and is utilized in synchronizing clocksignals applied to the packetized dynamic random access memory. Thepattern generator preferably comprises a register having a plurality ofinputs and outputs, and a clock terminal adapted to receive a clocksignal. The register shifts data applied on each of its inputs to acorresponding output responsive to the clock signals. A switch circuithas a plurality of first signal terminals coupled to receive latcheddigital signals from a latch which stores such signals in response to atransition of an internal clock signal. The switch circuit furtherincludes a plurality of second signal terminals coupled to thecorresponding inputs of the register, and a control terminal adapted toreceive a seed signal. The switch circuit couples each first signalterminal to a corresponding second signal terminal responsive to theseed signal going active. A logic circuit is coupled between theregister inputs and outputs, and has a terminal adapted to receive theseed signal. The logic circuit generates, when the seed signal isinactive, new expect data signals on its outputs responsive to currentexpect data signals provided on the register outputs. A synchronizationcircuit is coupled to the latch, a clock generator that generates theinternal clock signal, and the pattern generator, and operates incombination with the circuits to synchronize the internal clock signal.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023]FIG. 1 is a functional block diagram of a conventional SLDRAMpacketized memory device.

[0024]FIG. 2 is a table showing a typical command packet received by theSLDRAM of FIG. 1.

[0025]FIG. 3 is a diagram showing a repeating pseudo-random bitsequence, and illustrating conventional expected values for capturedgroups of that bit sequence, and actual values of captured groups for atime-shifted version of the applied bit sequence.

[0026]FIG. 4 is a functional block diagram of a synchronization circuitincluding a pattern generator according to one embodiment of the presentinvention.

[0027]FIG. 5 is a diagram illustrating expect data groups generated bythe pattern generator of FIG. 4.

[0028]FIG. 6 is a more detailed schematic of one embodiment of thepattern generator of FIG. 4.

[0029]FIG. 7 is a more detailed schematic illustrating one of the datageneration circuits of FIG. 6.

[0030]FIG. 8 is a more detailed schematic of the register of FIG. 7.

[0031]FIG. 9 is a logic diagram of one embodiment of the logic circuit610 of FIG. 6.

[0032]FIG. 10 is a more detailed schematic of one embodiment of theevaluation circuit of FIG. 4.

[0033]FIG. 11 is a more detailed schematic of one embodiment of thecompare circuit of FIG. 10.

[0034]FIG. 12 is a functional block diagram of a computer systemincluding a number of the SLDRAMs of FIG. 1, each containing the patterngenerator and synchronization circuit of FIG. 4.

DETAILED DESCRIPTION OF THE INVENTION

[0035]FIG. 4 is a functional block diagram of a synchronization circuit400 including a pattern generator 402 according to one embodiment of thepresent invention. Typically, the synchronization circuit 400 iscontained in the command buffer 46, address capture circuit 50, andclock generation circuits 40, 144 of the SLDRAM 16 of FIG. 1,and-operates during an initialization mode of the SLDRAM to synchronizethe clock signals CCLK, DCLK0, and DCLK1, as will be explained in moredetail below. During synchronization of the clock signals CCLK, CLK0,and DCLK1, the pattern generator 402 generates a sequence of expect datawords in response to a sample or seed group of bits latched on one ofthe terminals of the SLDRAM, as will also be described in more detailbelow. Components and signals that were previously described withreference to FIG. 1 have been given the same reference numbers in FIG.4, and will not be described in further detail.

[0036] In FIG. 4, only the components of the synchronization circuit 400required for synchronizing the command clock signal CCLK are shown andwill be described in further detail. As will be understood by oneskilled in the art, however, the synchronization circuit 400 alsoincludes analogous components for synchronizing the data clock signalsDCLK0 and DCLK1. For example, referring back to FIG. 1, the inputregisters 142 latch data packets applied on the data bus DQ in responseto clock signals generated by the clock generator 144 responsive to theselected one of the data clock signals DCLK0 and DCLK1, and these datapackets latched by the register are then compared by a correspondingevaluation circuit or circuits (not shown) in the synchronizationcircuit 400.

[0037] The synchronization circuit 400 includes a variable-phase clockgeneration circuit 404, which is part of the clock generation circuit 40of FIG. 1, and generates the internal clock signal ICLK in response tothe command clock signal CCLK. A more detailed description of oneembodiment of the variable-phase clock generation circuit 404 isdescribed in U.S. patent application Ser. No. 08/890,055 to Baker etal., which is incorporated herein by reference. The phase of theinternal command clock signal ICLK relative to the command clock signalCCLK is controlled by a phase command word CMDPH<0:3>developed by acontrol circuit 406. During the synchronization procedure, the controlcircuit 406 applies a number of control signals 414 to control theoperation of components of the synchronization circuit 400, and alsodetermines an optimum value for the phase command word CMDPH<0:3>, aswill be explained in more detail below.

[0038] The synchronization circuit 400 further includes a shift register408 receiving command packets CA<0:39> applied on the command-addressbus CA. The width of the command-address bus CA corresponds to the widthof the shift register 408, and the number of packet words CA<0:9> in thecommand packet CA<0:39> corresponds to the number of stages of the shiftregister 408. In the embodiment of FIG. 4, the shift register 408 hasfour stages, each of which is 10 bits wide. Thus, the shift register 408sequentially receives four 10-bit packet words CA<0:9>. Each of the fourpacket words CA<0:9> is shifted into the shift register 408, and fromone shift register stage to the next, responsive to each transition ofthe internal clock signal ICLK. The shift register 408 also latches theFLAG signal applied on the flag line 52 coincident with each packet wordCA<0:9>. Coincident with the start of each command packet CA<0:39>during normal operation of the memory device 16 (FIG. 1), the FLAGsignal transitions high for one-half the period of the internal clocksignal ICLK. The shift register 408 shifts this high FLAG signal througheach of the four stages of the shift register 12 responsive to eachtransition of the ICLK signal.

[0039] During normal operation, the latched high FLAG signal is used togenerate a plurality of control signals as it is shifted through stagesof the shift register 408. Once four packet words CA<0:9>, whichcorrespond to a single command packet CA<0:39>, are shifted into theshift register 408, the shift register generates a command triggersignal CTRIGGER. In response to the CTRIGGER signal, a storage register410 loads the 44-bit contents of the shift register 408 and thereaftercontinuously outputs these loaded words until new words are loaded inresponse to the next CTRIGGER signal. In the embodiment shown in FIG. 4in which four 10-bit packet words C<0:9> and 4 FLAG bits are shiftedinto the shift register 408, the storage register 410 receives andstores a 40-bit command word C<0:39> and a 4 bit flag-latched wordFLAT<0:3>. However, in the more general case, the shift register 408 hasN stages, each of which has a width of M bits, and the storage register410 loads an M*N bit command word.

[0040] The synchronization mode of the SLDRAM 16 is signaled by a FLAGsignal that is twice the width of the normal FLAG signal, i.e., adouble-width FLAG signal having a duration equal to the period of theICLK signal. In response to the double-width FLAG signal, the shiftregister 408 activates a calibration signal CAL, causing thesynchronization circuit 400 to execute a synchronization procedure tosynchronize the CCLK, DCLK0, and DCLK1 clock signals, as will beexplained in more detail below. Thus, there will be at least twotransitions of the ICLK signal during the double-width FLAG signal.During the synchronization procedure, the shift register 408 once againgenerates the CTRIGGER signal after four packet words CA<0:9> areshifted into the shift register 408. In response to the active CTRIGGERsignal, the storage register 410 again loads and outputs the latchedcommand packet CA<0:39> and flag-latched word FLAT<0:3>. The shiftregister 408 also applies the CAL and CTRIGGER signals to the controlcircuit 406, which utilizes the signals in controlling the operation ofcomponents in the circuit 400 during the synchronization mode, as willbe explained in more detail below.

[0041] One embodiment of the shift register 408 that may be utilized inthe synchronization circuit 400 is described in more detail in U.S.patent application No. 08/994,461 to Manning, which is incorporatedherein by reference. The detailed circuitry of the shift register 408will not be discussed in further detail since such circuitry andoperation is slightly tangential to the present invention. One skilledin the art will realize, however, the shift register 408 must be capablea latching packet words CA<0:9> received at very high rates duringoperation of the synchronization circuit 400, and during normaloperation of the memory device 16 containing the circuit 400. Forexample, in one embodiment the command clock CCLK has a frequency of 200MHz, requiring the shift register circuit 408 to store one packet wordCA<0:9> every 2.5 ns (i.e., one packet word in response to each fallingand rising edge of the CCLK signal).

[0042] The synchronization circuit 400 further includes an evaluationcircuit 412 that compares the command word C<0:39> and the flag-latchedword FLAT<0:3> output by the storage register 410 to an expected data orsynchronization sequence word SYNCSEQ<0:3> generated by the patterngenerator 402, and develops a command initialization results signalCINITRES in response to this comparison. The synchronization sequenceword SYNCSEQ<0:3> generated by the pattern generator 402 corresponds tothe expected values for the bits in the command word C<0:39> andflag-latched word FLAT<0:3> output by the storage register 410, as willbe described in more detail below. When the bits of the command wordC<0:39> and flag-latched word FLAT<0:3> have their expected valuesdetermined by the SYNCSEQ<0:3> word, the evaluation circuit 20 drivesthe CINITRES signal high, indicating the command packet CA<0:39> andlatched FLAG bits were successfully captured. In contrast, when at leastone of the bits in the command word C<0:39> or flag-latched wordFLAT<0:3> does not have its expected value determined by theSYNCSEQ<0:3> word, the evaluation circuit 412 drives the CINITRES signalinactive low, indicating the command packet CA<0:39> and latched FLAGbits were unsuccessfully captured. The control circuit 406 develops anumber of control signals 414 to control the operation of the evaluationcircuit 412 and other components in the synchronization circuit 400, aswill be explained in more detail below.

[0043] Before describing the overall operation of the synchronizationcircuit 400, the pattern generator 402 will be described in more detail.As previously mentioned, the pattern generator 402 generates theSYNCSEQ<0:3> word corresponding to expected values for the latchedcommand word CA<0:39> and flag-latched word FLAT<0:3> word. The controlcircuit 406 applies a seed signal SEED and complementary seed clocksignals SCLK, SCLK to the pattern generator 402. The pattern generator402 further receives a seed word SEED<0:3> corresponding to theflag-latched word FLAT<0:3> from the storage register 410. In operation,the pattern generator 402 operates in a seed mode to latch the appliedseed word SEED<0:3> when the SEED signal is active high. The patterngenerator 402 thereafter operates in a data generation mode when theSEED signal is inactive to generate a series of SYNCSEQ<0:3> wordsresponsive to the applied clock signals SCLK, SCLK, with the specificvalues for each of the SYNCSEQ<0:3> words in the series being determinedby the value of the applied SEED<0:3> word, as will now be explained inmore detail with reference to the diagram of FIG. 5. As previouslydescribed, during synchronization of the SLDRAM 16, a memory controller(not shown) applies the 15-bit pseudo-random bit sequence on each lineof the command-address bus CA, data bus DQ, and FLAG line 52. In FIG. 5,the 15 potential values for the 4-bit sequentially latched flag-latchedwords FLAT<0:3> are shown, and are designated FLAT₀<0:3>-FLAT₁₄<0:3>.These are the same as the capture groups C1-C15 of FIG. 3, and have beenlabeled FLAT₀<0:3>-FLAT₁₄<0:3> merely to indicate each capture groupcorresponds to a FLAT<0:3> word. In other words, the flag-latched wordsFLAT₀<0:3>-FLAT₁₄<0:3> correspond to the values of four consecutive FLAGbits sequentially latched by the shift register 408. As previouslydiscussed a FLAG bit is applied coincident with each packet wordCA<0:39>, and four packet words comprise a command packet CA<0:39>.Thus, for each of the flag-latched words FLAT₀<0:3>-FLAT₁₄<0:3> shown inFIG. 5, a corresponding command packet CA<0:39> has been latched.

[0044] As previously described the memory controller (not shown) placesthe synchronization circuit 400 in the synchronization mode of operationby applying the repeating 15-bit pseudo-random bit sequence for the FLAGbit as indicated in the first row of values for the flag-latched wordsFLAT₀<0:3>-FLAT₁₄<0:3>, which is labeled ideal FLAG data. As shown, thememory controller starts this 15-bit pseudo-random bit sequence byapplying 1111, then 0101, 1001, and so on as illustrated. Thus, thefirst row of FIG. 5 represents the ideal expected values for 15sequentially latched flag-latched words FLAT₀<0:3>-FLAT₁₄<0:3>. In otherwords, the memory controller initiates the 15-bit pseudo-random bitsequence by applying 1111 as the first four bits of the FLAG bit, so theideal value for the flag-latched word FLAT₀<0:3>is 1111. The next fourFLAG bits applied by the memory controller are 0101, so the ideal valuefor the flag-latched word FLAT₁<0:3>is 0101, and so on for each of theflag-latched words FLAT_(2<0:3 >-FLAT) ₁₄40:3>, as illustrated in thetop row of FIG. 5.

[0045] The second row of FIG. 5 illustrates the shifted version of therepeating 15-bit pseudo-random bit sequence applied on the FLAG line,which was previously discussed with reference to FIG. 3. With theshifted FLAG data pattern, the values for the flag-latched wordsFLAT₀<0:3>-FLAT₁₄<0:3> are as shown, and correspond to the ideal FLAGdata pattern shifted to the left by two bits. In other words, the firsttwo 1's of the ideal FLAG data pattern are not captured by the shiftregister 408 (FIG. 4), but instead the shift register 408 beginssuccessfully capturing the applied FLAG bit sequence starting with thethird 1, as indicated by the dotted line 500 in FIG. 5. As previouslydescribed, when the flag-latched words FLAT₀<0:3>-FLAT₁₄<0:3> have thevalues indicated in the shifted FLAG data pattern, a conventionalpattern recognition circuit determines the FLAG bit is being improperlylatched since none of the FLAT₁<0:3>-FLAT₁₄<0:3> words in the shiftedFLAG data pattern equals the corresponding word in the ideal FLAG datapattern as seen in FIG. 5.

[0046] The pattern generator 402 according to one aspect of the presentinvention eliminates the problem of capturing a shifted version of theideal FLAG sequence by utilizing the first-captured FLAT<0:3> word asthe initial value in the generated expected sequence of FLAT<0:3> words,and then generating the expected values for future FLAT<0:3> wordsrelative to this initial value. In other words, the pattern generator402 merely generates the ideal sequence of values, but starts generatingthis sequence with the value immediately after the value of the firstcaptured flag-latched word FLAT<0:3>. For example, assume the value ofFLAT₀<0:3> equals 1101, which corresponds to the word FLAT₈<0:3> in theideal sequence. In this situation, the pattern generator 402 generatesthe value 0110 for the SYNCSEQ<0:3> word, which corresponds to the valueof FLAT_(9<)0:3> in the ideal sequence. As seen in the shifted datasequence, FLAT_(2<)0:3> equals 0110 so the pattern generator hasgenerated the correct data. In this way, although the captured bitsequence is shifted relative to the ideal sequence, the patterngenerator 402 generates the correct expect data to determine whetherthis shifted bit sequence is being properly captured by the shiftregister 408 (FIG. 4) in response to the current phase of the ICLKsignal.

[0047] Several examples of the operation of the pattern generator 402are shown in the third row of FIG. 5, and these examples will now bedescribed in more detail to further explain the operation of the patterngenerator 402. In the first example, the first four FLAG bits capturedby the shift register 408 are 0110, and are labeled SEED1<0:3>. In thissituation, the SEED1<0:3> word is applied to the pattern generator 402and initializes or ‘seeds’ the pattern generator by giving the patterngenerator 402 a reference value from which to start generating futureexpected values for subsequent flag-latched words FLAT<0:3>. When theSEED1<0:3> word 0110 seeds the pattern generator 402, the patterngenerator generates the sequence of words 0100, 0111, 1010, and so on asthe expected values for subsequent flag-latched words FLAT<0:3>. As seenfrom the shifted FLAG data pattern, these subsequent values correspondto the actual values captured for subsequent flag-latched wordsFLAT<0:3>. In other words, when the SEED1<0:3> word seeds the patterngenerator 402, the pattern generator 402 generates values forsubsequently latched flag-latched words FLAT<0:3> that equal the correctvalues for such subsequent flag-latched words in the shifted FLAG datasequence. In the second example, the pattern generator 402 is seededwith a SEED2<0:3> word 1110. When the pattern generator 402 is seededwith the value 1110, it generates the values 1011, 0010, and so on forsubsequent values of the flag-latched words FLAT<0:3>, as illustrated.Once again, these subsequent generated values equal the correct valuesfor the shifted FLAG data sequence. Thus, even though the actual FLAGdata pattern being latched is shifted relative to the ideal FLAG datapattern, the pattern generator 402 generates correct values forsubsequent flag-latched words FLAT<0:3> in response to theSEED2<0:3>word 1110.

[0048] Referring back to FIG. 4, the overall operation of thesynchronization circuit 400 will now be described in more detail. Tosynchronize the command clock signal CCLK applied to the SLDRAM 16containing the synchronization circuit 400, a processor or memorycontroller (not shown in FIG. 4) applies the CCLK signal to the SLDRAM,and also applies the 15-bit pseudo-random bit sequence on each line ofthe command-address bus CA and on the FLAG line 52. At this point, thecontrol circuit 406 applies an initial phase command word CMDPH<0:3> tothe clock generator 404, which, in turn, generates the internal clocksignal ICLK having a phase relative to the CCLK signal determined bythis initial phase command word. At this point, the shift register 408latches packet words CA<0:9> applied on the command-address bus CA andFLAG bits applied on the line 52 in response to the ICLK signal. Inresponse to the two high FLAG bits, the shift register 408 activates thecalibration signal CAL, placing the synchronization circuit 400 in thesynchronization mode of operation. In response to the active CAL signal,the control circuit 406 generates phase command words CMDPH<0:3>,control signals 414, and applies the SEED and SCLK, SCLK signals to thepattern generator 402 to perform synchronization of the ICLK signal, aswill now be explained in more detail.

[0049] After receiving the active CAL signal, the control circuit 406activates the SEED signal placing the pattern generator 402 in the seedmode in anticipation of seeding the pattern generator. Recall, after thefour packet words CA<0:9> comprising a command packet CA<0:39> and thecoincident four FLAG bits have been latched by the shift register 408,the shift register outputs the latched command packet as the commandword C<0:39> and the four latched FLAG bits as the flag-latched wordFLAT<0:3>. The shift register 408 then pulses the CTRIGGER signalactive, causing the storage register 410 to load and output the commandword C<0:39> and flag-latched word FLAT<0:3>. This first capturedflag-latched word FLAT<0:3> output from the storage register 410 isapplied as the SEED<0:3> word to the pattern generator 402. At thispoint, the control circuit 406 clocks the pattern generator 402 with theSCLK, SCLK signals, causing the pattern generator 402 to latch theSEED<0:3> word. The control circuit 406 thereafter clocks the patterngenerator 402 in response to each CTRIGGER pulse, causing the patterngenerator 402 to generate a new synchronization sequence wordSYNCSEQ<0:3> word after each subsequent command packet CA<0:39> andcoincident four FLAG bits have been latched by the shift register 408.The control circuit 406 also activates the command initialization signalCINIT in response to the active CAL signal. In response to the CINITsignal, the evaluation circuit 412 is enabled in anticipation ofcomparing the C<0:39> and FLAT<0:3> words to their expected valuesdetermined by the SYNCSEQ<0:3> word, as will be described in more detailbelow.

[0050] While the pattern generator 402 is being seeded, the shiftregister 408 continues latching packet words CA<0:9> applied on thecommand-address bus CA and FLAG bits applied on the FLAG line 52 inresponse to the ICLK signal. After the next command packet CA<0:39> andaccompanying four FLAG bits have been latched by the shift register 408,the shift register once again generates the CTRIGGER pulse loading thelatched command word C<0:39> and flag-latched word FLAT<0:3> into thestorage register 410 which, in turn, outputs these words to theevaluation circuit 412. Before the control circuit 406 receives thesecond CTRIGGER pulse, it deactivates the SEED signal so that the nextvalue of the flag-latched word FLAT<0:3> is not loaded into the patterngenerator 402 as the SEED<0:3> word. At this point, the second commandword C<0:39> and second flag-latched word FLAT<0:3> are output by thestorage register 410 and applied to the evaluation circuit 412. Inresponse to the second CTRIGGER pulse, the control circuit 406 clocksthe pattern generator 402 with the SCLK, SCLK signals, causing thepattern generator 402 to generate the SYNCSEQ<0:3> word having a valuecorresponding to the expected values of the second latched C<0:39> andFLAT<0:3> words. Before the evaluation circuit 412 compares the secondlatched C<0:39> and FLAT<0:3> words to their expected values determinedby the SYNCSEQ<0:3> word, the control circuit resets the evaluationcircuit 412 which, in turn, drives the command initialization resultssignal CINITRES active high if that signal was low. The evaluationcircuit 412 is reset before the comparison of each new command wordC<0:39> and flag-latched word FLAT<0:3>.

[0051] The control circuit 406 then enables the evaluation circuit 412which, when enabled, compares the second latched command word C<0:39>and flag-latched word FLAT<0:3> to their expected values determined bythe SYNCSEQ<0:3> word. When the bits of the command word C<0:39> andflag-latched latched word FLAT<0:3> have their expected values, theevaluation circuit 412 maintains the CINITRES signal high, indicatingthe command packet CA<0:39> and latched FLAG bits were successfullycaptured. In contrast, when at least one of the bits in the command wordC<0:39> or flag-latched word FLAT<0:3> does not have its expected value,the evaluation circuit 412 drives the CINITRES signal inactive low,indicating the command packet CA<0:39> and latched FLAG bits were notsuccessfully captured.

[0052] The control circuit 406 stores the value of the CINITRES signaloutput by the evaluation circuit 412, and thereafter increments thevalue of the phase command word CMDPH<0:3> applied to the clockgenerator 404. In response to the incremented phase command wordCMDPH<0:3>, the clock generator generates the ICLK signal having a newphase relative to the CCLK signal corresponding to the new value of thephase command word. In response to the new ICLK signal, which has itsphase determined by the new phase command word CMDPH<0:3>, the shiftregister 408 latches the next four packet words CA<0:9> and fourcoincident FLAG bits and generates the CTRIGGER pulse after these wordshave been latched. Once again, the control circuit 406 toggles the SCLK,SCLK signals to clock the pattern generator 402 which, in turn,generates the new SYNCSEQ<0:3> word corresponding to the expected newvalues of the command word C<0:39> and flag-latched word FLAT<0:3>. Atthis point, control circuit 406 again resets and thereafter enables theevaluation circuit 412 which, when enabled, compares the new C<0:39> andFLAT<0:3> words to their expected values determined by the newSYNCSEQ<0:3> word and generates the resulting CINITRES signal on itsoutput, which is again stored by the control circuit 406.

[0053] The control circuit 406 continues incrementing the phase commandword CMDPH<0:3> and generating the appropriate control signals to storea number of values for the CINITRES signal, each value corresponding toparticular value of the phase command word CMDPH<0:3> (i.e., phase ofthe ICLK signal). After a predetermined number of values for theCINITRES signal have been stored, the control circuit 406 executes aphase selection procedure to select a final phase command wordCMDPH<0:3> from among the phase command words that resulted in thesuccessful capture of the command packet CA<0:39> and FLAG bits. In oneembodiment, the control circuit 406 stores sixteen values for theCINITRES signal, each corresponding to one of sixteen value for thephase command word CMDPH<0:3>, and selects the final phase command fromamong the ones of these sixteen values that resulted in the successfulcapture of the command packet CA<0:39> and FLAG bits. One procedure thatmay be executed by the control circuit 406 in determining the finalphase command word is described in the Baker et al. patent applicationthat was previously referenced, and which has been incorporated hereinby such reference. Upon determining the final phase command wordCMDPH<0:3>, the control circuit 406 stores this value and continuallyapplies it to the variable-phase clock generation circuit 404 duringnormal operation of the SLDRAM 16 (FIG. 1) containing thesynchronization circuit 400 and pattern generator 402.

[0054] One skilled in the art will realize that the procedure executedby the control circuit 406 in synchronizing the command clock signalCCLK may vary. For example, in the above-described procedure the controlcircuit 406 captures only one command packet CA<0:39> and flag-latchedword FLAT<0:3> at each phase of the ICLK signal. In another embodiment,the control circuit 406 performs a predetermined number of comparisonsat a given phase of the ICLK signal before storing a value for theCINITRES signal. In this embodiment, the control circuit 406 may, forexample, control components of the synchronization circuit 400 so thateight command words C<0:39> and flag-latched words FLAT<0:3> arecaptured and compared at each phase of the ICLK signal. When all eightof these comparisons indicate successful captures, the control circuit406 stores a “1” for the CINITRES signal at this phase. However, if anyof the comparisons at a given phase indicates an unsuccessful capture,the control circuit 406 stores a “0” for the CINITRES signal at thisphase. Once again, after sixteen, for example, CINITRES signals havebeen stored, the control circuit 406 determines the final phase commandword.

[0055] During synchronization of the data clock signals DCLK0 and DCLK1,the synchronization circuit 400 typically applies four latched bits onthe data line D0, which are designated a data-latched word DOL<0:3>, asthe SEED<0:3> word to the pattern generator 402 instead of theflag-latched word FLAT<0:3> as during synchronization of the CCLKsignal. In this way, the data applied on the data line DO of the databus DQ is utilized to seed the pattern generator 402 duringsynchronization of the data clock signals DCLK0 and DCLK1. In addition,the control circuit 406 deactivates the CINIT signal when either of thedata clocks DCLK0 and CDLK1 is being synchronized to thereby disable theevaluation circuit 412.

[0056]FIG. 6 is a more detailed functional block diagram of oneembodiment of the pattern generator 402 of FIG. 4. The pattern generator402 includes four data generation circuits 600 -606 receiving respectivebits of the SEED<0:3> word output by the storage register 410 (FIG. 4).The data generation circuits 600-606 further receive the SEED signaldirectly and through an inverter 608, and the clock signals SCLK, SCLKfrom the control circuit 406 (FIG. 4). A logic circuit 610 appliescomplementary pairs of flip data signals FLIP<0>, FLIP<0>-FLIP<3>,FLIP<3> to the data generation circuits 600-606, respectively, inresponse to an expect data word B<0:3> output collectively by the datageneration circuits 600-606, as will now be explained in more detailbelow. The expect data word B<0:3> includes both true and complementversions of each bit output by respective circuits 600-606, and isapplied through an inverter 612 to generate the synchronization sequenceword SYNCSEQ<0:3>. Although only a single inverter 612 is shown in FIG.6, one skilled in the art will realize there are actually four suchinverters, one for each bit of the expect data word B<0:3>.

[0057] In operation, the data generation circuits 600-606 operation inone of two modes, a seed mode and a generation mode. In the followingdescription, only the SCLK signal will be discussed, one skilled in theart understanding that the SCLK signal merely has the complementaryvalue of the SCLK signal. Initially, the control circuit 406 activatesthe SEED signal, placing the data generation circuits 600-606 in theseed mode of operation. In the seed mode, the data generation circuits600-606 latch the value of the applied SEED<0:3> word and shift thisword to their outputs as the expect data word B<0:3> responsive to theclock signals SCLK, SCLK. During the seed mode of operation, the valuesof the FLIP signals generated by the logic circuit 610 are ignored bythe data generation circuits 600-606.

[0058] The control circuit 406 thereafter deactivates the SEED signal,placing the data generation circuits 600-606 in the generation mode ofoperation. During the generation mode of operation, the current value ofthe expect data word B<0:3> is applied to the logic circuit 610 which,in turn, develops the FLIP signals having values that are determined bythe value of the expect data word B<0:3>. The FLIP signals are clockedinto the data generation circuits 600-606 in response to the appliedSCLK signal, and the data generation circuits 600-606 thereaftergenerate a new expect data word B<0:3> having a value determined by thevalues of the FLIP signals. This new expect data word B<0:3> is thenoutput through the inverter 612 as the synchronization sequence wordSYNCSEQ<0:3> and applied to the evaluation circuit 412, as previouslydescribed with reference to FIG. 4. In addition, the new expect dataword B<0:3> is also fed back to the logic circuit 610, which, in turn,once again develops new values for the FLIP signals in response to thisnew expect data word. The new values for the FLIP signals are once againclocked into the data generation circuits 600-606 in response to theSCLK signal, and the data generation circuits generate a new expect dataword B<0:3> having a value determined by the values of these new FLIPsignals. The new value for the expect data word B<0:3> is once againapplied through the inverter 612 to generate the new synchronizationsequence word SYNCSEQ<0:3>. This process continues as long as the clocksignal SCLK clocks the data generation circuits 600-606, or until theSEED signal again goes active, loading a new SEED<0:3> word into thedata generation circuits 600-606. In this situation, the patterngenerator 402 begins generating a new sequence of expect data wordsB<0:3> in response to this new SEED<0:3> word.

[0059] The overall operation of the pattern generator 402 and generaloperation of several components within that circuit have now beendescribed with reference to FIG. 6. At this point, several of thesecomponents will now be described in more detail with reference to FIGS.7-9. FIG. 7 is a schematic illustrating one embodiment of the datageneration circuit 600 of FIG. 6. The data generation circuits 600-606of FIG. 6 are typically identical, and thus, for the sake of brevity,only the data generation circuit 600 will be described in more detail.The data generation circuit 600 includes a register 700 that is clockedby the SCLK, SCLK signals. In response to these clock signals, theregister 700 shifts a signal applied on its input to its output todevelop the B<0> signal, and this signal is applied through an inverter702 to develop the B<0> signal. A transmission or pass gate 704 appliesthe SEED<0> bit to the input of the register 700 in response to theSEED, SEED signals. When the SEED and SEED signals are high and low,respectively, the pass gate 704 turns ON applying the SEED<0> signal tothe input of the register 700. The pass gate 704 turns OFF, isolatingthe SEED<0> signal from the register 700 when the SEED and SEED signalsare low and high, respectively.

[0060] A feedback coupling circuit 706 includes an output node 708 thatis also coupled to the input of the register 700. A pair of seriesconnected PMOS transistors 710 and 712 couple the expect data signalB<0> to the output node 708 in response to the FLIP<0> and SEED signalsapplied on their respective gates. When the FLIP<0> and SEED signals areboth low, the transistors 710 and 712 turn ON coupling the expect datasignal B<0> to the output node 708. If either of the FLIP<0> or SEEDsignals is high, the corresponding one of the transistors 710 and 712turns OFF isolating the B<0> signal from the output node 708. A PMOStransistor 714 receives the FLIP<0> signal on its gate and operates inconjunction with the transistor 712 to couple the expect data signalB<0> to the output node 708. When the FLIP<0> and SEED signals are bothlow, the transistors 712 and 714 turn ON coupling the expect data signalB<0> to the output node 708. If either of the SEED or FLIP<0> signalsare high, the corresponding one of the transistors 712 and 714 turnsOFF, isolating the expect data signal B<0> from the output node 708. Thefeedback coupling circuit 706 further includes three NMOS transistors716-720 coupled in the same way as the PMOS transistors 710-714,respectively, as shown. When the SEED and FLIP<0> signals are high, thetransistors 716 and 718 turn ON, coupling the expect data signal B<0> tothe output node 708. When the SEED and FLIP <0> signals are high, thetransistors 718 and 720 turn ON, coupling the expect data signal B<0> tothe output node 708.

[0061] In operation, the data generation circuit 600 operates in one oftwo modes, a seed mode and a data generation mode, as previouslydiscussed with reference to FIG. 6. During the seed mode, the SEED andSEED signals are high and low, respectively, turning ON the pass gate704 and thereby coupling the SEED<0> signal to the input of the register700. In addition, the high SEED signal and low SEED signal turn OFF thetransistors 712 and 718, respectively, isolating the output node 708from the remaining circuitry of the feedback coupling circuit 706. Atthis point, the register 700 is clocked by the SCLK, SCLK signals andshifts the SEED<0> signal applied on its input to its output as theexpect data signal B<0>. In this way, during the seed mode of operation,the SEED<0> bit is shifted to the output of the register 700 as thefirst expect data bit B<0>. The SEED and SEED signals thereafter go lowand high, respectively, initiating operation of the data generationcircuit 600 in the data generation mode.

[0062] During the data generation mode of operation, the feedbackcoupling circuit 706 couples either the expect data signal B<0> or itscomplement B<0> to the input of the register 700 in response to thevalues of the FLIP<0> and FLIP<0> signals, and the register 700 isclocked by the SCLK, SCLK signals to shift the signal on its input toits output as the new expect data signal B<0>, as will now be explainedin more detail. In the data generation mode, the SEED and SEED signalsare low and high, respectively, turning ON the transistors 712 and 718.When the transistors 712 and 718 are turned ON, the values of theFLIP<0> and FLIP<0> signals determine whether the expect data signalB<0> or B<0> is coupled to the output node 708 and thereby to the inputof the register 700. When the FLIP<0> and FLIP<0> signals are high andlow, respectively, the transistors 714 and 720 turn OFF and transistors710 and 716 turn ON. When transistors 714 and 720 turn OFF, the expectdata signal B<0> is isolated from the output node 708. In response tothe turned ON transistors 710 and 716, the expect data signal B<0> isapplied through both the series connected transistors 710,712 and716,718 to the output node 708 and is thus applied as the new input tothe register 700. As previously explained, the new expect data signalB<0> is thereafter shifted to the output of the register 700 as the newexpect data signal B<0> in response to the SCLK, SCLK signals. Thus,when the FLIP<0> and FLIP<0> signals are high and low, respectively, theexpect data signal B<0> is shifted to the output of the register 700 asthe new expect data signal B<0>. In other words, when the FLIP<0> andFLIP<0> signals are high and low, respectively, the new value for theexpect data signal B<0> is the complement of its previous value. Itshould be noted that in this situation the expect data signal B<0> iscoupled to the output node 708 through two pairs of series connectedtransistors, the PMOS series connected pair 710 and 712 and the NMOSconnected pair 716 and 718. This is done so that regardless of the valueof the expect data signal B<0>, the full voltage corresponding to thisvalue is coupled to the output node 708. which would not occur for oneof the logic levels of the signal B<0> if both NMOS and PMOS transistorswere not used, as will be understood by one skilled in the art.

[0063] When the FLIP<0> and FLIP<0> signals are low and high,respectively, the transistors 710 and 716 turn OFF, isolating the expectdata signal B<0> from the output node 708, and the transistors 714 and720 turn ON coupling the expect data signal B<0> through both the seriesconnected transistors 712,714 and 718,720 to the output node 708 andthereby to the input of the register 700. Thus, when the FLIP<0> andFLIP<0> signals are low and high, respectively, the current expect datasignal B<0> is applied to the input of the register 700 and thereaftershifted to the output of the register 700 as the new expect data signalB<0> in response to the SCLK, SCLK signals. In other words, when theFLIP<0> and FLIP<0> signals are low and high, respectively, the newvalue for the expect data signal B<0> is the same as its prior value. Inthis way, the data generation circuit 600 generates either a 0 or 1 forthe expect data signal B<0> as it is clocked by the SCLK, SCLK signals,with the value of the new expect data signal B<0> being determined bythe values of the FLIP<0> and FLIP<0> signals.

[0064]FIG. 8 is a detailed schematic of one embodiment of the register700 of FIG. 7. In the register 700, first and second pass gates 800 and802 are activated in a complementary manner in response to the clocksignals SCLK, SCLK. When the SCLK and SCLK signals are high and low,respectively, the pass gate 800 turns ON and pass gate 802 turns OFF,and the converse is true when the values of the clock signals SCLK. SCLKare complemented. When the pass gate 800 is activated, it couples theSLED<0> signal to an input of a latch 804 including cross-coupledinverters 806 and 808. The latch 804 latches its input to the value ofthe applied SEED<0> signal, and its output to the complement of thisvalue. When the pass gate 802 is activated, it applies the output of thelatch 804 to an input of a latch 810 including cross-coupled inverters812 and 814. The latch 810 latches its input to the value of a signalapplied on that input, and latches the expect data signal B<0> on itsoutput to the complement of the value on its input. A PMOS resettransistor 816 is coupled between the supply voltage source V_(CC) andthe input of the latch 810 and operates, when activated, to drive theinput of the latch 810 high, which, in turn, latches the expect datasignal B<0> low. In the embodiment of FIG. 8, however, the resettransistor 816 receives the supply voltage source V_(CC) on its gate,turning OFF the transistor 816 so that it does not effect operation ofthe register 700. In operation, the register 700 shifts the SEED<0>signal through the pass gate 800 to the latch 804 when the SCLK and SCLKsignals are high and low, respectively. When the SCLK and SCLK signalsgo low and high, respectively, the register 700 shifts the value storedin the latch 804 through the turned ON pass gate 802 to the latch 810and in this way shifts the SEED<0> signal to the output of the latch 810as the expect data signal B<0>.

[0065]FIG. 9 is a more detailed logic diagram of one embodiment of thelogic circuit 610 of FIG. 6. As previously described with reference toFIG. 6, the logic circuit 610 receives the current value of the expectdata word B<0:3> and generates the FLIP signals in response to thisexpect data word. Recall, the FLIP signals are utilized by the datageneration circuits 600-606 during their data generation mode ofoperation to generate new values for the expect data word B<0:3> inresponse to the previous value for the expect data word. In theembodiment of FIG. 9, the bits B<0> and B<0> generate the FLIP<3> andFLIP<3> signals, respectively. A pair of pass gates 900 and 902 operatein a complementary manner in response to the B<0> and B<0> signals toapply either the B<3> or B<3> signal directly and through an inverter904 to develop the FLIP<2> and FLIP<2>. A first group of NAND gates906-920 receive specific combinations of the true and complement bits ofthe expect data word B<0:3>, and generate respective outputs in responseto these signals. The outputs of the NAND gates 906-912 are combined bya NAND gate 922 having its output coupled directly and through aninverter 924 to develop the FLIP<1> and FLIP<1> signals. The group ofNAND gates 914-920 have their outputs combined by a NAND gate 926. Agroup of NAND gates 928-932 then combine the outputs of the NAND gates922 and 926 along with the expect data signals B<1> and B<1>, and theoutput of the NAND gate 932 is applied directly and through an inverter934 to develop the FLIP<0> and FLIP<0> signals.

[0066] The logic circuit 610 develops the FLIP signals having valuesthat cause the pattern generator 402 of FIG. 6 is generate a sequence ofexpect data words B<0:3> having values determined by the repeating15-bit pseudo-random bit sequence of Table 1. Referring back to Table 1,if the flag-latched word FLAT<0:3> applied as the SEED<0:3> word to thepattern generator 402 equals 0101, the logic circuit 610 generatesvalues for the FLIP signals causing the pattern generator 402 togenerate 1001 for the next value of the expect data word B<0:3> then0001 for the word B<0:3>, and so on as previously described. One skilledin the art will realize a myriad of alternative embodiments may beutilized for the logic circuit 610 in order to develop FLIP signalshaving values that cause the pattern generator 402 to generate expectdata words B<0:3> for this and other repeating bit sequences.

[0067]FIG. 10 illustrates one embodiment of the evaluation circuit 412of FIG. 4, which, as previously described, compares the command wordC<0:39> and flag-latched word FLAT<0:3> to expected values determined bythe SYNC.SEQ<0:3> word, and generates the CINITRES signal having a valueindicating the result of this comparison. The evaluation circuit 412includes a PMOS reset transistor 1000 coupled between a supply voltagesource V_(CC) and a sensing node 1002 and receiving an enablecalibration signal ENCAL from the control circuit 406 applied on itsgate. A latch 1004 including two cross-coupled inverters 1006, 1008 hasits input coupled to the sensing node 1002 and its output coupled to aninput of an inverter 1010 which develops the CINITRES signal on itsoutput in response to the output of the latch 1004.

[0068] The evaluation circuit 412 further includes a compare circuit1012 coupled between the sensing node 1002 and an enable node 1014. Thecompare circuit 1012 receives the latched command word C<0:39>andflag-latched word FLAT<0:3> corresponding to the captured command packetreceived on the command-address bus CA and latched FLAG bits received onthe flag line 52, as previously described. In addition, the comparecircuit 1012 further receives a plurality of signals derived from thesynchronization sequence word SYNCSEQ<0:3> generated by the patterngenerator 402. More specifically, each bit of the synchronizationsequence word SYNCSEQ<0:3> is coupled through a respective inverter 1016to generate a complementary synchronization sequence word SYNCSEQ<0:3>which, in turn, is further coupled through a respective inverter 1018 togenerate a buffered synchronization sequence word SYNCSEQBUF<0:3>. TheSYNCHSEQ<0:3> and SYNCHSEQBUF<0:3> words are utilized by the comparecircuit 1012 in determining whether each of the bits in the command wordC<0:39> and latched FLAG word FLAT<0:3> has its expected value, as willbe explained in more detail below.

[0069] The evaluation circuit 412 further includes an enable transistor1020 coupled between the enable node 1014 and ground. An inverter 1028has its output applied through a transmission gate 1022 to the gate ofthe enable transistor 1020. The control circuit 406 applies a commandinitialization signal CINIT directly and through an inverter 1024 to thecontrol terminals of the transmission gate 1022. The output of theinverter 1024 is further applied to a gate of a transistor 1026 coupledbetween the gate of the enable transistor 1020 and ground. When theCINIT signal goes active high, the inverter 1024 drives its output lowturning OFF the transistor 1026 and turning ON the transmission gate1022 and thereby coupling the output of the inverter 1028 to the gate ofthe enable transistor 1020. Thus, when the CINIT signal is active high,the level at the output of the inverter 1028 determines whether theenable transistor 1020 turns ON or OFF. The control circuit 406 appliesan initialization strobe signal INITSTRB through an inverter 1032 to aninput of a pulse generator 1030 which, in turn, outputs a pulse signalto the input of the inverter 1028. When the INITSTRB signal goes activehigh, the inverter 1032 drives its output low causing the pulsegenerator 1030 to apply a low pulse signal on the input of the inverter1028, which, in turn, drives its output high for the duration of thispulse. This high output from the inverter 1028 is coupled through thetransmission gate 1022, when activated, turning ON the enable transistor1022.

[0070] The output of the inverter 1028 is further coupled through aninverter 1034 to one input of a NAND gate 1036 receiving the ENCALsignal on a second input. The output of the NAND gate 1036 is applieddirectly and through an inverter 1038 to enable terminals of a buffer1040 coupled between the output of the latch 1004 and the sensing node1002 as shown. When the output of the NAND gate 1036 goes low, thebuffer 1040 is enabled and applies the inverse of the signal on theoutput of the latch 1004 on the sensing node 1002. If the output of theNAND gate 1036 is high, the buffer 1040 is disabled, placing its outputin a high impedance state.

[0071]FIG. 11 is a more detailed schematic of the compare circuit 1012of FIG. 10 including a plurality of bit compare circuits BCC1-BCCN.There is one bit compare circuit BCC1-BCCN for each bit compared by thecompare circuit 1012. In the embodiment of FIG. 11, the compare circuit1012 includes 44 bit compare circuit BCC1-BCC44, one for each bit of thecommand word C<0:39> and flag-latched word FLAT<0:3>. All the bitcompare circuits BCC1-BCCN are identical, and thus, for the sake ofbrevity, only the bit compare circuit BCC1 will be described in moredetail. The bit compare circuit BCC1 receives the bit C<0> of thecommand word C<0:39>, and applies this bit through a first inverter 1100to an input of a first transmission gate 1102, and through the firstinverter 1100 and a second inverter 1104 to the input of a secondtransmission gate 1106. The transmission gates 1102 and 1106 receive theSYNCSEQ<0> and SYNCSEQBUF<0> signals on their respective controlterminals as shown, and are activated in a complementary manner inresponse to the values of these signals. When the SYNCSEQ<0> signal ishigh and SYNCSEQBUF<0> signal is low, the transmission gate 1102 turnsON and transmission gate 1106 turns OFF, and when the signals SYNCSEQ<0>and SYNCSEQBUF<0> are low and high, respectively, the transmission gate1106 turns ON and transmission gate 1102 turns OFF. The outputs of thetransmission gates 1102 and 1106 are applied to a gate of a comparisontransistor 1108 coupled between the sensing node 1002 and the enablenode 1014.

[0072] In operation, the bit compare circuit BCC1 compares the value ofthe bit C<0> to its expected value determined by the values of the bitsSYNCSEQ<0> and SYNCSEQBUF<0> and activates the compare transistor 1108when the bit C<0> does not have its expected value, as will now beexplained in more detail. The pattern generator 402 (see FIG. 4)determines an expected value for the command bit C<0> corresponding toone of the bits in the SYNCSEQ<0:3> word from the flag-latched wordFLAT<0:3>, as previously described. When the expected value of thecommand bit C<0>is high, the pattern generator 402 drives the SYNCSEQ<0>and SYNCSEQBUF<0> signals high and low, respectively, turning ONtransmission gate 1102 and turning OFF transmission gate 1106. Thecommand bit C<0> is then applied through the inverter 1100 and throughthe turned ON transmission gate 1102 to the gate of the comparetransistor 1108. If the command bit C<0> is high as expected, theinverter 1100 applies a low signal through the transmission gate 1102 tothe gate of the compare transistor 1108, turning OFF this transistor. Incontrast, if the command bit C<0> is a binary 0 instead of a binary 1 asexpected, the inverter 1100 drives its output high and this high outputis applied through the transmission gate 1102 to the gate of thetransistor 1108. In response to the high signal on its gate, thetransistor 1108 turns ON, coupling the sensing node 1002 to the enablenode 1014.

[0073] When the expected value of the command bit C<0> is a binary 0,the pattern generator 402 drives the SYNCSEQ<0> and SYNCSEQBUF<0>signals low and high, respectively, turning ON the transmission gate1106 and turning OFF the transmission gate 1102. The command bit C<0> isthen applied through the inverters 1100 and 1104 and through the turnedON transmission gate 1106 to the gate of the compare transistor 1108. Ifthe command bit C<0> is a binary 0 as expected, the inverter 1104 drivesits output low, turning OFF the transistor 1108 and isolating thesensing node 1002 from the enable node 1014. In contrast, if the commandbit C<0> is not a binary 0 as expected but is instead a binary 1, theinverter 1104 drives its output high, turning ON the transistor 1108which couples the sensing node 1002 to the enable node 1014.

[0074] Returning now to FIG. 10, the overall operation of the evaluationcircuit 412 in comparing the value of each bit in the command wordC<0:39> and flag-latched word FLAT<0:3> to its expected value will nowbe described in more detail. As previously described with reference toFIG. 4, the control circuit 406 applies the CINIT, ENCAL, and INITSTRBsignals (i.e., indicated as control signals 414 in FIG. 4) to controloperation of the evaluation circuit 412. When the CINIT signal isinactive low, the transmission gate 1022 turns OFF and the transistor1026 turns ON. The turned ON transistor 1026 couples the gate of theenable transistor to ground, turning OFF the enable transistor 1020which isolates the enable node 1014 from ground. In this situation, theevaluation circuit 412 is deactivated and does not evaluate the commandword C<0:39> and flag-latched word FLAT<0:3>.

[0075] The evaluation circuit 412 is enabled when the CINIT signal isactive high turning ON the transmission gate 1022 and enable transistor1020, which couples the enable node 1014 to approximately ground. TheENCAL signal goes inactive low before evaluation of a particular commandword C<0:39> and flag-latched word FLAT<0:3>. In response to the lowENCAL signal, the transistor 1000 turns ON, coupling the sensing node1002 to approximately the supply voltage V_(CC). In response to the highon the sensing node 1002, the latch 1004 drives its output low and theinverter 1010, in turn, drives the CINITRES signal on its output high.At this point, the INITSTRB signal is inactive low and the pulsegenerator 1030 drives its output high causing the inverter 1028 to driveits output low. The low output from the inverter 1028 is applied throughthe turned ON transmission gate 1022 to the gate of the enabletransistor 1020, turning OFF this transistor and thereby isolating theenable node 1014 from ground. It should be noted that when the ENCALsignal goes inactive low, the NAND gate 1036 deactivates the buffer 1040enabling the transistor 1000 to more easily drive the sensing node 1002high.

[0076] Once the ENCAL signal has gone inactive low, disabling andresetting the evaluation circuit 412, the ENCAL signal thereafter goesactive high, enabling the evaluation circuit 412 to begin comparinglatched command words C<0:39> and flag-latched words FLAT<0:3>. At thispoint, the pattern generator 402 applies the generated synchronizationsequence word SYNCSEQ<0:3> to the evaluation circuit 412 and thecorresponding SYNCSEQ <0:3> and SYNCSEQBUF<0:3> words are, in turn,applied to the compare circuit 1012, indicating the expected value foreach of the bits in the latched C<0:39> and FLAT<0:3> words. At thispoint, the expected data in the form of the SYNCSEQ<0:3> andSYNCSEQBUF<0:3> words and the latched data in the form of the C<0:39>and FLAT<0:3> words are applied to the compare circuit 1012, but thecompare circuit 1012 is not yet enabled since the transistor 1020 isturned OFF. The INITSTRB signal then goes active high and the pulsegenerator 1030, in turn, generates the low pulse on its output, causingthe inverter 1028 to pulse its output high and thereby turn ON theenable transistor 1020 so that the compare circuit 1012 compares thelatched command word C<0:39> and flag-latched word FLAT<0:3> to theexpected data.

[0077] As previously described with reference to FIG. 11, when each bitof the command word C<0:39> and flag-latched word FLAT<0:3> has itsexpected value, the corresponding compare transistor 1108 coupledbetween the sensing node 1002 and enable node 1014 does not turn ON.Thus, when the latched command words C<0:39> and FLAT<0:3> have theirexpected values, none of the transistors 1108 in the compare circuit1012 turns ON and the sensing node 1002 remains at approximately thesupply voltage V_(CC). Accordingly, when the words C<0:39> and FLAT<0:3>have their expected values, the voltage on the sensing node 1002 remainshigh such that the latch 1004 maintains its output low and the inverter1010 continues driving the CINITRES signal active high indicating thelatched words C<0:39> and FLAT<0:3> were successfully captured. If anyof the bits in the words C<0:39> and FLAT<0:3> does not have itsexpected value, the corresponding compare transistor 1108 turns ON,coupling the sensing node 1002 to approximately ground. When the sensingnode 1002 goes low, the latch 1004 drives its output high causing theinverter 1010 to drive the CINITRES signal low, indicating the C<0:39>and FLAT<0:3> words were not successfully captured.

[0078] It should be noted that the low pulse on the output of the pulsegenerator 1030 results in the inverter 1034 also pulsing its output low,which causes the NAND gate 1036 to drive its output high for theduration of this pulse. As previously described, when the output of theNAND gate 1036 goes high, the buffer 1040 is disabled to enable thesensing node 1002 to be more easily driven low if any of the bits werenot successfully captured. After the end of the pulse generated by thepulse generator 1030, the NAND gate 1036 again drives its output lowenabling the buffer 1040 to drive the sensing node 1002 to its desiredvalue. As will be understood by one skilled in the art, the sensing node1002 may present a rather large capacitance due to all the componentscoupled in parallel to this node, and the buffer 1040 includestransistors sized such that the buffer 1040 may drive this relativelylarge capacitance to its desired voltage and in this way assists theinverter 1006, which typically has smaller sized transistors.

[0079] An example of a computer system 900 using the synchronous linkarchitecture is shown in FIG. 12. The computer system 900 includes aprocessor 912 having a processor bus 914 coupled through a memorycontroller 918 and system memory bus 923 to three packetized orsynchronous link dynamic random access memory (“SLDRAM”) devices 916a-c. The computer system 910 also includes one or more input devices920, such as a keypad or a mouse, coupled to the processor 912 through abus bridge 922 and an expansion bus 924, such as an industry standardarchitecture (“ISA”) bus or a peripheral component interconnect (“PCI”)bus. The input devices 920 allow an operator or an electronic device toinput data to the computer system 900. One or more output devices 930are coupled to the processor 912 to display or otherwise output datagenerated by the processor 912. The output devices 930 are coupled tothe processor 912 through the expansion bus 924, bus bridge 922 andprocessor bus 914. Examples of output devices 930 include printers and avideo display units. One or more data storage devices 938 are coupled tothe processor 912 through the processor bus 914, bus bridge 922, andexpansion bus 924 to store data in or retrieve data from storage media(not shown). Examples of storage devices 938 and storage media includefixed disk drives floppy disk drives, tape cassettes and compact-diskread-only memory drives.

[0080] In operation, the processor 192 sends a data transfer command viathe processor bus 914 to the memory controller 918, which, in turn,communicates with the memory devices 916 a-c via the system memory bus,923 by sending the memory devices 916 a-c command packets that containboth control and address information. Data is coupled between the memorycontroller 918 and the memory devices 916 a-c through a data bus portionof the system memory bus 922. During a read operation, data istransferred from the SLDRAMs 916 a-c over the memory bus 923 to thememory controller 918 which, in turn, transfers the data over theprocessor bus 914 to the processor 912. The processor 912 transferswrite data over the processor bus 914 to the memory controller 918which, in turn, transfers the write data over the system memory bus 923to the SLDRAMs 916 a-c. Although all the memory devices 916 a-c arecoupled to the same conductors of the system memory bus 923, only onememory device 916 a-c at a time reads or writes data, thus avoiding buscontention on the memory bus 923. Bus contention is avoided by each ofthe memory devices 916 a-c on the system memory 923 having a uniqueidentifier, and the command packet contains an identifying code thatselects only one of these components.

[0081] The computer system 900 typically also includes a number of othercomponents and signal lines that have been omitted from FIG. 12 in theinterests of brevity For example, the memory devices 916 a-c alsoreceive a command clock signal CCLK to provide internal timing signals,data clock signals DCLK0 and DCLK1 for clocking data into and out of thememory devices 916, and a FLAG signal signifying the start of a commandpacket and utilized to place the memory devices 916 in synchronizationmode, as previously explained.

[0082] It is to be understood that even though various embodiments andadvantages of the present invention have been set forth in the foregoingdescription, the above disclosure is illustrative only, and changes maybe made in detail, and yet remain within the broad principles of theinvention. For example, many of the components described above may beimplemented using either digital or analog circuitry, or a combinationof both, and also, where appropriate, may be realized through softwareexecuting on suitable processing circuitry. Therefore, the presentinvention is to be limited only by the appended claims. Appl. No. AttyDkt # Applicant Filed Title 09/146,860 500444.01 Troy A. 03 Sep. 1998Method and (660073.691) Manning Apparatus for Generating Expect DataFrom a Captured Bit Pattern, and Memory Device Using Same

1. A method for generating expect digital signals for a series ofapplied digital signals having a known sequence to determine if applieddigital signals are being properly captured, comprising: capturing afirst group of the applied digital signals; generating a group of expectdigital signals from the captured first group of applied digitalsignals; capturing a second group of the applied digital signals afterthe first group; and determining the second group of applied digitalsignals was properly captured when the second captured group of applieddigital signals corresponds to the generated group of expect digitalsignals.
 2. The method of claim 1 wherein the series of applied digitalsignals comprises a 15 bit pseudo-random bit sequence of digitalsignals.
 3. The method of claim 2 wherein the 15 bit pseudo-random bitsequence comprises the repeating bit sequence of “11110101001000.” 4.The method of claim 1 wherein each group comprises four data signals. 5.The method of claim 1 wherein each group of applied digital signalsincludes four digital signals, and generating the group of expectdigital signals comprises: storing the four -digital signals of thefirst group on respective first through fourth output nodes; developinga first logic signal from the signal on the four output nodes;developing a second logic signal from three of the four signals on thefour output nodes; coupling either the digital signal on the firstoutput node or the complement of this digital signal to a first storagenode responsive to the first logic signal to develop a first expectdigital signal on the first storage node; coupling either the digitalsignal on the second output node or the complement of this digitalsignal to a second storage node responsive to the second logic signal todevelop the second expect data signal on the second storage node;coupling either the data signal on the third output node or thecomplement of this data signal to a third storage node responsive to thedata signal on the first output node and the data signal on the fourthoutput node to develop the third expect data signal on the third storagenode; coupling either the data signal on the fourth output node or thecomplement of this data signal to a fourth storage node responsive tothe data signal on the first output node to develop the fourth expectdata signal on the fourth storage node; and coupling the first throughfourth storage nodes to the first through fourth output nodes,respectively, to apply the four expect data signals on these respectivenodes.
 6. A method for synchronizing a clock signal applied on a clockterminal of an SLDRAM, comprising: placing the SLDRAM in asynchronization mode; applying the clock signal; generating an internalclock signal responsive to the external clock signal, the internal clocksignal having a phase relative to the external clock signal; applying arepeating sequence of digital signals on each of a plurality of dataterminals of the SLDRAM, each sequence having a known pattern; capturinga group of digital signals on each of the data terminals responsive tothe internal clock signal; generating a series of expect data groups,each expect data group including a plurality of expect digital signalshaving values determined in response to the values of expect digitalsignals in the preceding expect data group, and the values of thedigital signals in the first expect data group being determinedresponsive to digital signals from one of the captured groups of digitalsignals; capturing a subsequent group of digital signals applied on thedata terminals responsive to the internal clock signal; comparing thedigital signals in the subsequent group to the expect digital signals inthe corresponding expect data group, and determining the subsequentgroup was successfully captured when each of the digital signals thesubsequent group has its expected value; storing the results of thiscomparison; adjusting the phase of the clock signal; repeating the actsof capturing a subsequent group of digital signals through adjusting thephase of the internal clock signal until a predetermined number ofphases have been utilized for the internal clock signal; and selecting aphase of the internal clock signal from one of stored phases thatsuccessfully captured the applied digital signals.
 7. The method ofclaim 6 wherein applying a repeating sequence of digital signals on eachof a plurality of data terminals comprises applying a true repeating 15bit pseudo-random bit sequence on every other data terminal and applyingthe complement of this true sequence on those data terminals notreceiving the true sequence.
 8. The method of claim 6 wherein each groupcomprises four digital signals.
 9. The method of claim 6 wherein thedigital signals from one of the captured groups of digital signals usedto determine the digital signals in the first expect data group comprisefour captured digital signals applied sequentially on a FLAG terminal ofthe SLDRAM.
 10. The method of claim 6 wherein comparing the digitalsignals comprises comparing the digital signals in a predeterminednumber of subsequent groups to their corresponding expect digitalsignals for each phase of the internal clock signal, and determiningcaptures for a respective phase were successful only when the digitalsignals in all subsequent groups have their corresponding expectedvalues.
 11. A method for generating an expect data pattern from anapplied bit stream having a known pattern, comprising capturing a firstgroup of bits from the applied bit stream, and generating an expectedgroup of bits having values determined by the values of the capturedfirst group of bits.
 12. The method of claim 11 wherein the applied bitstream comprises a 15-bit pseudo-random bit sequence.
 13. The method ofclaim 12 wherein the 15 bit pseudo-random bit sequence comprises therepeating bit sequence of “111101011001000.”
 14. The method of claim 11wherein the captured first group of bits includes 4 bits.
 15. A methodof adaptively adjusting the phase of an internal clock signal relativeto an external clock signal, the internal clock signal triggering alatch to store a digital signal, the method comprising: repetitivelyapplying digital signals to the latch in a known repeating sequence;storing a first group of digital signals in the latch responsive to theinternal clock signal having a first phase; generating expected valuesfor a next group of digital signals to be stored in the latch responsiveto the stored first group of digital signals; storing a second group ofdigital signals in the latch responsive to the internal clock signalhaving the first phase; comparing the digital signals of the secondgroup to their expected values to determine if the stored digitalsignals were successfully captured by the latch, and storing the resultsof this comparison; repeating the acts of repetitively applying digitalsignals to comparing the digital signals for a plurality of phases ofthe internal clock signal; and selecting a phase of the clock signalthat caused the latch to store digital signals having the expectedvalues.
 16. The method of claim 15 wherein repetitively applying digitalsignals comprises applying a repeating 15 bit pseudo-random bit sequenceof digital signals.
 17. The method of claim 16 wherein the 15 bitpseudo-random bit sequence comprises the repeating bit sequence of“111101011001000.”
 18. The method of claim 15 wherein each groupcomprises four digital signals.
 19. The method of claim 15 whereingenerating the expected values for a next group of digital signals to bestored in the latch responsive to the stored first group of digitalsignals and storing a second group of digital signals in the latchresponsive to the internal clock signal having the first phase areperformed at the same time.
 20. A method of adaptively adjusting thephase of an internal clock signal relative to an external clock signal,the internal clock signal triggering a latch to store a digital signal,the method comprising: repetitively applying digital signals to thelatch in a known repeating sequence; storing a first group of digitalsignals in the latch responsive to the internal clock signal having afirst phase; generating an expect group of digital signals in responseto the values of the stored first group of digital signals; storing anext group of digital signals in the latch responsive to the internalclock signal having the first phase; comparing the digital signals ofthe next group to their expected values to determine if the storeddigital signals were successfully captured by the latch, and storing theresults of this comparison; adjusting the phase of the internal clocksignal; generating a next expect group of digital signals in response tothe values of the current expect group of digital signals; storing anext group of digital signals in the latch responsive to the internalclock signal having the adjusted phase; comparing the digital signals ofthe next group to their expected values to determine if the storeddigital signals were successfully captured by the latch, and storing theresults of this comparison; repeating adjusting the phase of theinternal clock signal to comparing the digital signals of the next groupfor a plurality of phases of the internal clock signal; and selecting aphase of the internal clock signal that caused the latch to storedigital signals having the expected values.
 21. The method of claim 20wherein generating a next expect group of digital signals occurssequentially responsive to the next group of digital signals beingstored in the latch.
 22. The method of claim 20 wherein repetitivelyapplying digital signals comprises applying a repeating 15 bitpseudo-random bit sequence of digital signals.
 23. The method of claim22 wherein the 15 bit pseudo-random bit sequence comprises the repeatingbit sequence of “111101011001000.”
 24. A pattern generator thatgenerates expect signals for a repeating bit sequence, comprising: aregister having a plurality of inputs and outputs, and a clock terminaladapted to receive a clock signal, the register shifting data applied oneach of its inputs to a corresponding output responsive to the clocksignals; a switch circuit having a plurality of first signal terminalsadapted to receive respective data input signals, a plurality of secondsignal terminals coupled to corresponding inputs of the register, and acontrol terminal adapted to receive a seed signal, the switch circuitcoupling each first signal terminal to a corresponding second signalterminal responsive to the seed signal being active; and a logic circuitcoupled between the register inputs and outputs, and having a terminaladapted to receive the seed signal, the logic circuit generating, whenthe seed signal is inactive, new expect digital signals on the registerinputs responsive to current expect digital signals provided on theregister outputs.
 25. The pattern generator of claim 24 wherein theregister comprises a plurality of individual register circuits coupledbetween each register input and output, each register circuitcomprising: a first pass gate having an input, output, and controlterminals adapted to receive respective complementary clock signals; afirst latch having an input coupled to the output of the first pass gateand having an output; a second pass gate having an input, output, andcontrol terminals adapted to receive the respective complementary clocksignals; a second latch having an input coupled to the output of thesecond pass gate and having an output; and a reset switch having signalterminals coupled between the input of the second latch and a supplyvoltage source, and having a control terminal adapted to receive a resetsignal.
 26. The pattern generator of claim 24 wherein the switch circuitincludes a plurality of pass gates, coupled between respectivecorresponding first and second signal terminals, and each havingcomplementary control terminals adapted to receive respective true andcomplement seed signals.
 27. The pattern generator of claim 24 whereinthe logic circuit includes four outputs, and comprises a plurality oflogic gates interconnected to develop as the expect digital signals allpossible 4 bit combinations for the 15 bit pseudo-random bit sequence1111 0101 1001 000, these fifteen possible 4 bit combinations being1111, 0101, 1001, 0001, 1110, 1011, 0010, 0011, 1101, 0110, 0100, 0111,1010, 1100, and
 1000. 28. The pattern generator of claim 24 wherein thelogic circuit comprises: a combinational logic circuit having aplurality of inputs adapted to receive current expect digital signalsfrom the register outputs and developing a plurality of flip signalsresponsive to the current expect digital signals; and a plurality ofcoupling circuits, each coupling circuit having an input coupled to acorresponding one of the register outputs, an output coupled to thecorresponding register input, a first control terminal coupled to thecombinational logic circuit, and a second control terminal adapted toreceive the seed signal, the coupling circuit operable in a first modewhen the seed signal is inactive to develop on its output either theexpect data signal applied on its input or the complement of the expectdata signal applied on its input responsive to a corresponding one ofthe flip signals, and operable in a second mode when the seed signal isactive to isolate its input from its output.
 29. The pattern generatorof claim 28 wherein each of the coupling circuits comprises: an inverterhaving an input coupled to the corresponding register output, and anoutput; an output node coupled to the input of the correspondingregister input; a first switch having a first signal terminal coupled tothe output of the inverter, a second signal terminal, and a controlterminal adapted to receive the complement of the corresponding one ofthe flip signals; a second switch having a first signal terminal coupledto the second signal terminal of the first switch, a second signalterminal coupled to the output node, and a control terminal adapted toreceive the seed signal; and a third switch having a first signalterminal coupled to the register input and a second signal terminalcoupled to the second signal terminal of the first switch, and a controlterminal adapted to receive the corresponding flip signal.
 30. Thepattern generator of claim 29 wherein each of the first, second, andthird switches is a PMOS transistor, and the coupling circuit furthercomprises three NMOS transistors coupled in the same way as the threePMOS transistors, each of the NMOS transistors adapted to receive on itsgate the complement of the signal applied to the gate of thecorresponding one of the PMOS transistors.
 31. An integrated circuithaving a plurality of external terminals adapted to receive respectivesignals, comprising: electronic circuitry having inputs coupled to atleast some of the external terminals and outputs coupled to at leastsome of the external terminals, the electronic circuitry generatingsignals on its outputs responsive to signals on its inputs to execute adesired function; a clock terminal adapted to receive an external clocksignal; a clock generator circuit having an input coupled to the clockterminal, and developing an internal clock signal having a phaserelative to the external clock signal in response to a phase command; alatch coupled to at least some of the external terminals and the clockgenerator circuit, the latch storing digital signals applied on theexternal terminals responsive to the internal clock signal; a patterngenerator that generates expect data for a repeating bit sequenceapplied on the external terminals, comprising, a register having aplurality of inputs and outputs, and a clock terminal adapted to receivea clock signal, the register shifting data applied on each of its inputsto a corresponding output responsive to the clock signals; a switchcircuit having a plurality of first signal terminals coupled to receivelatched digital signals from the latch, a plurality of second signalterminals coupled to corresponding inputs of the register, and a controlterminal adapted to receive a seed signal, the switch circuit couplingeach first signal terminal to a corresponding second signal terminalresponsive to the seed signal being active; a logic circuit coupledbetween the register inputs and outputs, and having a terminal adaptedto receive the seed signal, the logic circuit generating, when the seedsignal is inactive, new expect digital signals on the register inputsresponsive to current expect digital signals provided on the registeroutputs; and a synchronization circuit coupled to the latch, clockgenerator, and pattern generator, the synchronization circuit, during asynchronization mode of the integrated circuit, activating the seedsignal to seed the pattern generator with a data pattern captured by thelatch, and thereafter deactivating the seed signals, sequentiallyadjusting the phase command, and comparing the digital signals stored bythe latch to expected values developed by the pattern generator, thesynchronization circuit determining an optimum phase command from theresults of the comparisons and applying that phase command to the clockgenerator during normal operation of the electronic circuitry.
 32. Theintegrated circuit of claim 31 wherein the register comprises aplurality of individual register circuits coupled between each registerinput and output, each register circuit comprising: a first pass gatehaving an input, output, and control terminals adapted to receiverespective complementary clock signals; a first latch having an inputcoupled to the output of the first pass gate and having an output; asecond pass gate having an input, output, and control terminals adaptedto receive the respective complementary clock signals; a second latchhaving an input coupled to the output of the second pass gate and havingan output; and a reset switch having signal terminals coupled betweenthe input of the second latch and a supply voltage source, and having acontrol terminal adapted to receive a reset signal.
 33. The integratedcircuit. of claim 31 wherein the switch circuit includes a plurality ofpass gates, each pass gate coupled between a corresponding input andoutput, and having complementary control terminals adapted to receiverespective true and complement seed signals.
 34. The integrated circuitof claim 31 wherein the logic circuit includes four outputs, andcomprises a plurality of logic gates interconnected to develop as theexpect digital signals all possible 4 bit combinations for the 15 bitpseudo-random bit sequence 1111 0101 1001 000, these fifteen possible 4bit combinations being 1111, 0101, 1001, 0001, 1110, 1011, 0010, 0011,1101, 0110, 0100, 0111, 1010, 1100, and
 1000. 35. The integrated circuitof claim 31 wherein the logic circuit comprises: a combinational logiccircuit having a plurality of inputs adapted to receive current expectdigital signals from the register outputs and developing a plurality offlip signals responsive to the current expect digital signals; and aplurality of coupling circuits, each coupling circuit having an inputcoupled to a corresponding one of the register outputs, an outputcoupled to the corresponding register input, a first control terminalcoupled to the combinational logic circuit, and a second controlterminal adapted to receive the seed signal, the coupling circuitoperable in a first mode when the seed signal is inactive to develop onits output either the expect data signal applied on its input or thecomplement of the expect data signal applied on its input responsive toa corresponding one of the flip signals, and operable in a second modewhen the seed signal is active to isolate its input from its output. 36.The integrated circuit of claim 35 wherein each of the coupling circuitscomprises: an inverter having an input coupled to the correspondingregister output, and an output; an output node coupled to the input ofthe corresponding register input; a first switch having a first signalterminal coupled to the output of the inverter, a second signalterminal, and a control terminal adapted to receive the complement ofthe corresponding one of the flip signals; a second switch having afirst signal terminal coupled to the second signal terminal of the firstswitch, a second signal terminal coupled to the output node, and acontrol terminal adapted to receive the seed signal; and a third switchhaving a first signal terminal coupled to the register input and asecond signal terminal coupled to the second signal terminal of thefirst switch, and a control terminal adapted to receive thecorresponding flip signal.
 37. The integrated circuit of claim 36wherein each of the first, second, and third switches is a PMOStransistor, and the coupling circuit further comprises three NMOStransistors coupled in the same way as the three PMOS transistors, eachof the NMOS transistors adapted to receive on its gate the complement ofthe signal applied to the gate of the corresponding one of the PMOStransistors.
 38. A packetized dynamic random access memory, comprising:a clock generator circuit controlling the phase of an internal clocksignal relative to an external clock signal responsive to a phasecommand signal; at least one array of memory cells adapted to store dataat a location determined by a row address and a column address; a rowaddress circuit adapted to receive and decode the row address, andselect a row of memory cells corresponding to the row address responsiveto a first set of command signals; a column address circuit adapted toreceive or apply data to one of the memory cells in the selected rowcorresponding to the column address responsive to a second set ofcommand signals; a data path circuit adapted to couple data between anexternal terminal and the column address circuit responsive to a thirdset of command signals; a command buffer receiving command packets andinitialization packets having a predetermined value, the command bufferincluding a latch storing each of the received packets responsive to atransition of the internal clock signal, the command buffer furthergenerating a respective command words and initialization wordscorresponding to each received command packet and initialization packet,respectively; a pattern generator that generates expect data for arepeating bit sequence applied on external terminals of the packetizeddynamic random access memory, comprising, a register having a pluralityof inputs and outputs, and a clock terminal adapted to receive a clocksignal the register shifting data applied on each of its inputs to acorresponding output responsive to the clock signals, a switch circuithaving a plurality of first signal terminals coupled to receive latcheddigital signals from the latch, a plurality of second signal terminalscoupled to corresponding inputs of the register, and a control terminaladapted to receive a seed signal, the switch circuit coupling each firstsignal terminal to a corresponding second signal terminal responsive tothe seed signal being active, a logic circuit coupled between theregister inputs and outputs, and having a terminal adapted to receivethe seed signal, the logic circuit generating, when the seed signal isinactive, new expect digital signals on the register inputs responsiveto current expect digital signals provided on the register outputs; anda synchronization circuit coupled to the latch in the command buffer,clock generator, and pattern generator, the synchronization circuit,during a synchronization mode of the packetized dynamic random accessmemory, activating the seed signal to seed the pattern generator with adata pattern captured by the latch, and thereafter deactivating the seedsignals, sequentially adjusting the phase command, and comparing thedigital signals stored by the latch to expected values developed by thepattern generator, the synchronization circuit determining an optimumphase command from the results of the comparisons and applying thatphase command to the clock generator during normal operation of thepacketized memory device.
 39. The packetized dynamic random accessmemory of claim 38 wherein the register comprises a plurality ofindividual register circuits coupled between each register input andoutput, each register circuit comprising: a first pass gate having aninput, output, and control terminals adapted to receive respectivecomplementary clock signals; a first latch having an input coupled tothe output of the first pass gate and having an output; a second passgate having an input, output, and control terminals adapted to receivethe respective complementary clock signals; a second latch having aninput coupled to the output of the second pass gate and having anoutput; and a reset switch having signal terminals coupled between theinput of the second latch and a supply voltage source, and having acontrol terminal adapted to receive a reset signal.
 40. The packetizeddynamic random access memory of claim 38 wherein the switch circuitincludes a plurality of pass gates, each pass gate coupled between acorresponding input and output, and having complementary controlterminals adapted to receive respective true and complement seedsignals.
 41. The packetized dynamic random access memory of claim 39wherein the logic circuit includes four outputs, and comprises aplurality of logic gates interconnected to develop as the expect digitalsignals all possible 4 bit combinations for the 15 bit pseudo-random bitsequence 111101011001000, these fifteen possible 4 bit combinationsbeing 1111, 0101, 1001, 0001, 1110, 1011, 0010, 0011, 1101, 0110, 0100,0111, 1010, 1100, and
 1000. 42. The packetized dynamic random accessmemory of claim 38 wherein the logic circuit comprises: a combinationallogic circuit having a plurality of inputs adapted to receive currentexpect digital signals from the register outputs and developing aplurality of flip signals responsive to the current expect digitalsignals; and a plurality of coupling circuits, each coupling circuithaving an input coupled to a corresponding one of the register outputs,an output coupled to the corresponding register input, a first controlterminal coupled to the combinational logic circuit, and a secondcontrol terminal adapted to receive the seed signal, the couplingcircuit operable in a first mode when the seed signal is inactive todevelop on its output either the expect data signal applied on its inputor the complement of the expect data signal applied on its inputresponsive to a corresponding one of the flip signals, and operable in asecond mode when-the seed signal is active to isolate its input from itsoutput.
 43. The packetized dynamic random access memory of claim 42wherein each of the coupling circuits comprises: an inverter having aninput coupled to the corresponding register output, and an output; anoutput node coupled to the input of the corresponding register input; afirst switch having a first signal terminal coupled to the output of theinverter, a second signal terminal, and a control terminal adapted toreceive the complement of the corresponding one of the flip signals; asecond switch having a first signal terminal coupled to the secondsignal terminal of the first switch, a second signal terminal coupled tothe output node, and a control terminal adapted to receive the seedsignal; and a third switch having a first signal terminal coupled to theregister input and a second signal terminal coupled to the second signalterminal of the first switch, and a control terminal adapted to receivethe corresponding flip signal.
 44. The packetized dynamic random accessmemory of claim 43 wherein each of the first, second, and third switchesis a PMOS transistor, and the coupling circuit further comprises threeNMOS transistors coupled in the same way as the three PMOS transistors,each of the NMOS transistors adapted to receive on its gate thecomplement of the signal applied to the gate of the corresponding one ofthe PMOS transistors.
 45. A computer system, comprising: a processorhaving a processor bus; an input device coupled to the processor throughthe processor bus adapted to allow data to be entered into the computersystem; an output device coupled to the processor through the processorbus adapted to allow data to be output from the computer system; and adynamic random access memory coupled to the processor bus adapted toallow data to be stored, adapted to receive a plurality of input signalsand generate a plurality of output signals on respective, externallyaccessible terminals, the dynamic random access memory, comprising, aclock generator circuit controlling the phase of an internal clocksignal relative to an external clock signal responsive to a phasecommand signal; at least one array of memory cells adapted to store dataat a location determined by a row address and a column address; a rowaddress circuit adapted to receive and decode the row address, andselect a row of memory cells corresponding to the row address responsiveto a first set of command signals; a column address circuit adapted toreceive or apply data to one of the memory cells in the selected rowcorresponding to the column address responsive to a second set ofcommand signals; a data path circuit adapted to couple data between anexternal terminal and the column address circuit responsive to a thirdset of command signals; a command buffer receiving command packets andinitialization packets having a predetermined value, the command bufferincluding a latch storing each of the received packets responsive to atransition of the internal clock signal, the command buffer furthergenerating a respective command words and initialization wordscorresponding to each received command packet and initialization packet,respectively; a pattern generator that generates expect data for arepeating bit sequence applied on external terminals of the packetizeddynamic random access memory, comprising, a register having a pluralityof inputs and outputs, and a clock terminal adapted to receive a clocksignal, the register shifting data applied on each of its inputs to acorresponding output responsive to the clock signals, a switch circuithaving a plurality of first signal terminals coupled to receive latcheddigital signals from the latch, a plurality of second signal terminalscoupled to corresponding inputs of the register, and a control terminaladapted to receive a seed signal, the switch circuit coupling each firstsignal terminal to a corresponding second signal terminal responsive tothe seed signal being active, a logic circuit coupled between theregister inputs and outputs, and having a terminal adapted to receivethe seed signal, the logic circuit generating, when the seed signal isinactive, new expect digital signals on the register inputs responsiveto current expect digital signals provided on the register outputs; anda synchronization circuit coupled to the latch in the command buffer,clock generator, and pattern generator, the synchronization circuit,during a synchronization mode of the packetized dynamic random accessmemory, activating the seed signal to seed the pattern generator with adata pattern captured by the latch, and thereafter deactivating the seedsignals, sequentially adjusting the phase command, and comparing thedigital signals stored by the latch to expected values developed by thepattern generator, the synchronization circuit determining an optimumphase command from the results of the comparisons and applying thatphase command to the clock generator during normal operation of thepacketized memory device.
 46. The computer system of claim 45 whereinthe register comprises a plurality of individual register circuitscoupled between each register input and output, each register circuitcomprising: a first pass gate having an input, output, and controlterminals adapted to receive respective complementary clock signals; afirst latch having an input coupled to the output of the first pass gateand having an output; a second pass gate having an input, output, andcontrol terminals adapted to receive the respective complementary clocksignals; a second latch having an input coupled to the output of thesecond pass gate and having an output; and a reset switch having signalterminals coupled between the input of the second latch and a supplyvoltage source, and having a control terminal adapted to receive a resetsignal.
 47. The computer system of claim 45 wherein the switch circuitincludes a plurality of pass gates, each pass gate coupled between acorresponding input and output, and having complementary controlterminals adapted to receive respective true and complement seedsignals.
 48. The computer system of claim 46 wherein the logic circuitincludes four outputs, and comprises a plurality of logic gatesinterconnected to develop as the expect digital signals all possible 4bit combinations for the 15 bit pseudo-random bit sequence 1111 01011001 000, these fifteen possible 4 bit combinations being 1111, 0101,1001, 0001, 1110, 1011, 0010, 0011, 1101, 0110, 0100, 0111, 1010, 1100,and
 1000. 49. The computer system of claim 45 wherein the logic circuitcomprises: a combinational logic circuit having a plurality of inputsadapted to receive current expect digital signals from the registeroutputs and developing a plurality of flip signals responsive to thecurrent expect digital signals; and a plurality of coupling circuits,each coupling circuit having an input coupled to a corresponding one ofthe register outputs, an output coupled to the corresponding registerinput, a first control terminal coupled to the combinational logiccircuit, and a second control terminal adapted to receive the seedsignal, the coupling circuit operable in a first mode when the seedsignal is inactive to develop on its output either the expect datasignal applied on its input or the complement of the expect data signalapplied on its input responsive to a corresponding one of the flipsignals, and operable in a second mode when the seed signal is active toisolate its input from its output.
 50. The computer system of claim 49wherein each of the coupling circuits comprises: an inverter having aninput coupled to the corresponding register output, and an output; anoutput node coupled to the input of the corresponding register input; afirst switch having a first signal terminal coupled to the output of theinverter, a second signal terminal, and a control terminal adapted toreceive the complement of the corresponding one of the flip signals; asecond switch having a first signal terminal coupled to the secondsignal terminal of the first switch, a second signal terminal coupled tothe output node, and a control terminal adapted to receive the seedsignal; and a third switch having a first signal terminal coupled to theregister input and a second signal terminal coupled to the second signalterminal of the first switch, and a control terminal adapted to receivethe corresponding flip signal.
 51. The computer system of claim 50wherein each of the first, second, and third switches is a PMOStransistor, and the coupling circuit further comprises three NMOStransistors coupled in the same way as the three PMOS transistors, eachof the NMOS transistors adapted to receive on its gate the complement ofthe signal applied to the gate of the corresponding one of the PMOStransistors.